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A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology.

W. Chen, C. Tsai, C. Chang, Y. Peng, F. Hsueh, T. Yu, J. Chien, W. Huang, C. Lu, M. Lin, C. Fu, S. Yang, C. Wong, W. Chen, C. Wen, L. Wang, and C. Pu. CICC, page 1-4. IEEE, (2010)

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Chien-Wen Hung

Wen-tsung Hung

Wen-ling Huang

Wen-chih Huang

Wen-Hong Huang

Other publications of authors with the same name

Uniprocessor Scheduling Strategies for Self-Suspending Task Systems.G. von der Brüggen, W. Huang, J. Chen, and C. Liu. RTNS, page 119-128. ACM, (2016)On the Formalism and Properties of Timing Analyses in Real-Time Embedded Systems.J. Chen, W. Huang, G. von der Brüggen, K. Chen, and N. Ueter. A Journey of Embedded and Cyber-Physical Systems, page 37-55. Springer, (2021)State of the art for scheduling and analyzing self-suspending sporadic real-time tasks.J. Chen, G. von der Brüggen, W. Huang, and C. Liu. RTCSA, page 1-10. IEEE Computer Society, (2017)A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology.W. Chen, C. Tsai, C. Chang, Y. Peng, F. Hsueh, T. Yu, J. Chien, W. Huang, C. Lu, M. Lin and 7 other author(s). CICC, page 1-4. IEEE, (2010)Analysis of Impulsive Interference in Digital Audio Broadcasting Systems in Electric Vehicles.C. Chen, W. Huang, B. Karanov, A. Young, Y. Wu, and W. van Houtum. CoRR, (2024)A 56Gb/s PAM-4 Receiver with Voltage Pre-Shift CTLE and 10-Tap DFE of Tap-1 Speculation in 7nm FinFET.W. Chen, S. Yang, Y. Shih, W. Huang, C. Tsai, and K. Hsieh. VLSI Circuits, page 272-. IEEE, (2019)A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application.M. Lin, C. Tsai, C. Chang, W. Huang, Y. Hsu, S. Yang, C. Fu, M. Chou, T. Huang, C. Chen and 5 other author(s). IEEE J. Solid State Circuits, 49 (4): 1063-1074 (2014)TFRP: An efficient microaggregation algorithm for statistical disclosure control.C. Chang, Y. Li, and W. Huang. J. Syst. Softw., 80 (11): 1866-1878 (2007)Resource-Oriented Partitioned Scheduling in Multiprocessor Systems: How to Partition and How to Share?W. Huang, M. Yang, and J. Chen. RTSS, page 111-122. IEEE Computer Society, (2016)A 4-to-18GHz Active Poly Phase Filter Quadrature Clock Generator with Phase Error Correction in 5nm CMOS.W. Chen, C. Wen, C. Fu, T. Tsai, Y. Chen, W. Huang, C. Tsai, A. Loke, and C. Kenny. VLSI Circuits, page 1-2. IEEE, (2020)

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Disambiguation of "Huang, Wen-Hung"

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A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology.

Please choose a person to relate this publication to

Chien-Wen Hung

Wen-tsung Hung

Wen-ling Huang

Wen-chih Huang

Wen-Hong Huang

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Huang, Wen-Hung"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology.

Please choose a person to relate this publication to

Chien-Wen Hung

Wen-tsung Hung

Wen-ling Huang

Wen-chih Huang

Wen-Hong Huang

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology.