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Disambiguation of "Hwang, Wei"

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On-demand memory sub-system for multi-core SoCs.

, , and . SoCC, page 122-127. IEEE, (2011)

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Wei Wei

Wei Wei

Wei Wei

Wei Wei

Wei Wei

 

Other publications of authors with the same name

Area-power-efficient 11-bit hybrid dual-Vdd ADC with self-calibration for neural sensing application., , , , and . SoCC, page 18-23. IEEE, (2016)All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction., , , , , , and . VLSI-DAT, page 1-4. IEEE, (2015)An all-digital power management unit with 90% power efficiency and ns-order voltage transition time for DVS operation in low power sensing SoC applications., , , , , and . ISCAS, page 1370-1373. IEEE, (2015)A noise-tolerant matchline scheme with XOR-based conditional keeper for energy-efficient TCAM., , and . ISCAS, IEEE, (2006)Low quiescent current variable output digital controlled voltage regulator., and . ISCAS, page 609-612. IEEE, (2010)Low Power Pre-Comparison Scheme for NOR-Type 10T Content Addressable Memory., , and . APCCAS, page 1301-1304. IEEE, (2006)A comparison of dual-rail pass transistor logic families in 1.5V, 0.18µm CMOS technology for low power applications., and . ACM Great Lakes Symposium on VLSI, page 101-106. ACM, (2000)An Energy-Efficient 3D Cross-Ring Accelerator With 3D-SRAM Cubes for Hybrid Deep Neural Networks., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 11 (4): 776-788 (2021)Memory-Centric Fusion-based CNN Accelerator with 3D-NoC and 3D-DRAM., , , , and . ISOCC, page 169-170. IEEE, (2022)A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control., , , , , , , , , and 9 other author(s). SoCC, page 197-200. IEEE, (2011)