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F3: Cutting the last wire - Advances in wireless power.

, , , , , и . ISSCC, стр. 1-2. IEEE, (2015)

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Petra Sandner

Thorben Sandner

Dietmar Sandner

Edgar Sandner

Ludwig Sandner

 

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F5: Frequency generation and clock distribution., , , , , , , и . ISSCC, стр. 508-509. IEEE, (2013)A 6bit, 1.2GSps Low-Power Flash-ADC in 0.13µm Digital CMOS., , , , и . DATE, стр. 223-226. IEEE Computer Society, (2004)A fully integrated analog front-end macro for cable modem applications in 0.18-μm CMOS., , , , , , и . IEEE J. Solid State Circuits, 37 (7): 866-873 (2002)Global Optimization of Reconfigurable Switched Capacitor DC-DC Converters., , , , , и . ICECS, стр. 522-525. IEEE, (2019)A subpicosecond jitter PLL for clock generation in 0.12-μm digital CMOS., и . IEEE J. Solid State Circuits, 38 (7): 1275-1278 (2003)Quadrature VCOs Based on Coupled PLLs., , , и . ISCAS, стр. 2140-2143. IEEE, (2007)ESD-protected CMOS 3-5 GHz wideband LNA+PGA design for UWB., , , , , и . ESSCIRC, стр. 219-222. IEEE, (2005)Switched capacitor DC-DC converter in 65nm CMOS technology with a peak efficiency of 97%., , , и . ISCAS, стр. 1351-1354. IEEE, (2011)A fully integrated 2.4-GHz LC-VCO frequency synthesizer with 3-ps jitter in 0.18-μm standard digital CMOS copper technology., , , , , и . IEEE J. Solid State Circuits, 37 (7): 959-962 (2002)Fast and robust level shifters in 65 nm CMOS., , , , , и . ESSCIRC, стр. 195-198. IEEE, (2011)