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Statistical Characterization of Library Timing Performance., , , , и . PATMOS, том 4148 из Lecture Notes in Computer Science, стр. 468-476. Springer, (2006)P.SIZE: a sizing aid for optimized designs., , и . EURO-DAC, стр. 160-165. IEEE Computer Society Press, (1992)Product On-Chip Process Compensation for Low Power and Yield Enhancement., , , , , , , , , и 3 other автор(ы). PATMOS, том 5953 из Lecture Notes in Computer Science, стр. 247-255. Springer, (2009)Delay bound based CMOS gate sizing technique., , , , и . ISCAS (5), стр. 189-192. IEEE, (2004)Synchronised 4-Phase Resonant Power Clock Supply for Energy Efficient Adiabatic Logic., , , , и . ICRC, стр. 1-6. IEEE, (2017)Statistical timing characterization., , , и . ISSoC, стр. 1-4. IEEE, (2012)Circuit sizing method under delay constraint., , , и . ISCAS, IEEE, (2006)CMOS Gate Sizing under Delay Constraint., , , , и . PATMOS, том 2799 из Lecture Notes in Computer Science, стр. 60-69. Springer, (2003)Performance Metric Based Optimization Protocol., , , , и . PATMOS, том 3254 из Lecture Notes in Computer Science, стр. 100-109. Springer, (2004)A mixed-signal oscillatory neural network for scalable analog computations in phase domain., , , , , , и . Neuromorph. Comput. Eng., 3 (3): 34004 (сентября 2023)