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Disambiguation of "Azémard, Nadine"

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A mixed-signal oscillatory neural network for scalable analog computations in phase domain.

, , , , , , and . Neuromorph. Comput. Eng., 3 (3): 34004 (September 2023)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Nadine Jerusel

Analyse und Prognose der Krankheitslast Osteoporose - attributabler proximaler Femurfrakturen in Deutschland. Uni Leipzig, (2009)

Nadine Ziemert

Identification and characterisation of ribosomal biosynthesis pathways of two cyclic peptides from cyanobacteria. HU Berlin, (2009)

Nadine Sonnenberg

Theoretische Untersuchungen zur Adsorption von Arzneistoffen an Mikrokristalliner Celulose. Uni Düsseldorf, (2008)

Nadine Pohl

Nadine Willner

 

Other publications of authors with the same name

Delay bound based CMOS gate sizing technique., , , , and . ISCAS (5), page 189-192. IEEE, (2004)Statistical Characterization of Library Timing Performance., , , , and . PATMOS, volume 4148 of Lecture Notes in Computer Science, page 468-476. Springer, (2006)Product On-Chip Process Compensation for Low Power and Yield Enhancement., , , , , , , , , and 3 other author(s). PATMOS, volume 5953 of Lecture Notes in Computer Science, page 247-255. Springer, (2009)Synchronised 4-Phase Resonant Power Clock Supply for Energy Efficient Adiabatic Logic., , , , and . ICRC, page 1-6. IEEE, (2017)P.SIZE: a sizing aid for optimized designs., , and . EURO-DAC, page 160-165. IEEE Computer Society Press, (1992)A mixed-signal oscillatory neural network for scalable analog computations in phase domain., , , , , , and . Neuromorph. Comput. Eng., 3 (3): 34004 (September 2023)Delay-power performance analysis., , , and . ICECS, page 1543-1546. IEEE, (1999)Gate Sizing for Low Power Design., , and . VLSI-SOC, volume 218 of IFIP Conference Proceedings, page 301-312. Kluwer, (2001)Statistical timing characterization., , , and . ISSoC, page 1-4. IEEE, (2012)Circuit sizing method under delay constraint., , , and . ISCAS, IEEE, (2006)