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Architecture design with STT-RAM: Opportunities and challenges.

P. Chi, S. Li, Y. Cheng, Y. Lu, S. Kang, and Y. Xie. ASP-DAC, page 109-114. IEEE, (2016)

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Yuanqing Gao

Yuanqing Guo

Cheng-Yung Cheng

I-Fen Cheng

Ying Min Cheng

Other publications of authors with the same name

Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part II: CNT Interconnect Optimization.R. Chen, L. Chen, J. Liang, Y. Cheng, S. Elloumi, J. Lee, K. Xu, V. Georgiev, K. Ni, P. Debacker and 2 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 30 (4): 440-448 (2022)Zero-skew Clock Network Synthesis for Monolithic 3D ICs with Minimum Wirelength.W. Wang, V. Pavlidis, and Y. Cheng. ACM Great Lakes Symposium on VLSI, page 399-404. ACM, (2020)AES design improvement towards information safety.L. Wu, X. Wang, X. Zhao, Y. Cheng, D. Su, A. Chen, Q. Shi, and M. Tehranipoor. ISCAS, page 1706-1709. IEEE, (2016)PDG: A Prefetcher for Dynamic Graph Updating.X. Zhang, C. Liu, J. Ni, Y. Cheng, L. Zhang, H. Li, and X. Li. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (4): 1246-1259 (April 2024)OPT: Optimal Proposal Transfer for Efficient Yield Optimization for Analog and SRAM Circuits.Y. Liu, G. Dai, Y. Cheng, W. Kang, and W. Xing. ICCAD, page 1-9. IEEE, (2023)Quantitative evaluation of reliability and performance for STT-MRAM.L. Zhang, A. Todri-Sanial, W. Kang, Y. Zhang, L. Torres, Y. Cheng, and W. Zhao. ISCAS, page 1150-1153. IEEE, (2016)TOTAL: Multi-Corners Timing Optimization Based on Transfer and Active Learning.W. Xing, Z. Xing, R. Lu, Z. Wang, N. Xu, Y. Cheng, and W. Zhao. DAC, page 1-6. IEEE, (2023)ODESY: a novel 3T-3MTJ cell design with optimized area DEnsity, scalability and latencY.L. Xue, Y. Cheng, J. Yang, P. Wang, and Y. Xie. ICCAD, page 118. ACM, (2016)DOVA: A Dynamic Overwriting Voltage Adjustment for STT-RAM L1 Cache.J. Chen, K. Liu, X. Guo, P. Girard, and Y. Cheng. ISQED, page 408-414. IEEE, (2020)Architecture design with STT-RAM: Opportunities and challenges.P. Chi, S. Li, Y. Cheng, Y. Lu, S. Kang, and Y. Xie. ASP-DAC, page 109-114. IEEE, (2016)

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Disambiguation of "Cheng, Yuanqing"

copy delete add this publication to your clipboard
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Architecture design with STT-RAM: Opportunities and challenges.

Please choose a person to relate this publication to

Yuanqing Gao

Yuanqing Guo

Cheng-Yung Cheng

I-Fen Cheng

Ying Min Cheng

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Cheng, Yuanqing"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Architecture design with STT-RAM: Opportunities and challenges.

Please choose a person to relate this publication to

Yuanqing Gao

Yuanqing Guo

Cheng-Yung Cheng

I-Fen Cheng

Ying Min Cheng

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Architecture design with STT-RAM: Opportunities and challenges.