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Reliability-aware Co-synthesis for Embedded Systems., , , , and . VLSI Signal Processing, 49 (1): 87-99 (2007)Exploring memory controller configurations for many-core systems with 3D stacked DRAMs., , , and . ISQED, page 565-570. IEEE, (2015)Crosstalk-Aware Energy Efficient Encoding for Instruction Bus through Code Compression., and . SoCC, page 193-196. IEEE, (2006)Leakage Optimized DECAP Design for FPGAs., , , , and . APCCAS, page 960-963. IEEE, (2006)Nonfullerene Polymer Solar Cells Based on a Main-Chain Twisted Low-Bandgap Acceptor with Power Conversion Efficiency of 13.2\%, , , , , , , , , and 1 other author(s). ACS Energy Letters, 3 (7): 1499--1507 (May 2018)Effect of Power Optimizations on Soft Error Rate., , , , and . VLSI-SoC (Selected Papers), volume 200 of IFIP, page 1-20. Springer, (2003)Discriminative Reverse Sparse Tracking via Weighted Multitask Learning., , , , and . IEEE Trans. Circuits Syst. Video Techn., 27 (5): 1031-1042 (2017)Design space exploration for 3D architectures., , , and . JETC, 2 (2): 65-103 (2006)Understanding the trade-offs in multi-level cell ReRAM memory design., , , , and . DAC, page 108:1-108:6. ACM, (2013)Technology, CAD tools, and designs for emerging 3D integration technology., , and . ACM Great Lakes Symposium on VLSI, page 1-2. ACM, (2008)