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Disambiguation of "González, Alejandro F."

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CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differentiaI-resistance devices.

, , , and . IEEE J. Solid State Circuits, 36 (6): 924-932 (2001)

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Alejandro Gomez Gonzalez

Alejandro Gomez Gonzalez

José González

Margarita González

Lillian González

 

Other publications of authors with the same name

Compact Signed-Digit Adder Using Multiple-Valued Logic., and . ARVLSI, page 96-113. IEEE Computer Society, (1997)CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differentiaI-resistance devices., , , and . IEEE J. Solid State Circuits, 36 (6): 924-932 (2001)Multiple-Valued Signed-Digit Adder Using Negative Differential-Resistance Devices., and . IEEE Trans. Computers, 47 (9): 947-959 (1998)Redundant arithmetic, algorithms and implementations., and . Integr., 30 (1): 13-53 (2000)Circuit Design using Resonant Tunneling Diodes., , , and . VLSI Design, page 501-506. IEEE Computer Society, (1998)A 250-MHz, 32-bit quantum MOS correlator prototype., , , and . ICECS, page 1501-1504. IEEE, (2001)A prototyping technique for large-scale RTD-CMOS circuits., , , and . ISCAS, page 635-638. IEEE, (2000)Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder Based on Negative Differential-Resistance Devices., , , and . ISMVL, page 323-330. IEEE Computer Society, (2000)A spatio-temporal access method based on snapshots and events., , , , and . GIS, page 115-124. ACM, (2005)Comparison of Bistable Circuits Based on Resonant-Tunneling Diodes., and . VLSI Design, page 493-492. IEEE Computer Society, (2003)