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Disambiguation of "Yuan, Jiann-Shiun"

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Statistical sensitivity simulation for integrating design and testing of MOSFET integrated circuits.

, , , and . VTS, page 104-108. IEEE Computer Society, (1991)

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Jiann-Sheng Wu

Jiann-Trzuo Lin

Jiann-Chyuan Lin

Xiugan Yuan

Li Yuan

 

Other publications of authors with the same name

Optimization of NULL convention self-timed circuits., , , , and . Integr., 37 (3): 135-165 (2004)Substrate Bias Effect on Dynamic Characteristics of a Monolithically Integrated GaN Half-Bridge., , , , and . IRPS, page 1-5. IEEE, (2020)Emerging Technology-Based Design of Primitives for Hardware Security., , , , , , , , and . ACM J. Emerg. Technol. Comput. Syst., 13 (1): 3:1-3:19 (2016)NULL convention multiply and accumulate unit with conditional rounding, scaling, and saturation., , , , and . J. Syst. Archit., 47 (12): 977-998 (2002)Improving power-awareness of pipelined array multipliers using two-dimensional pipeline gating and its application on FIR design., , and . Integr., 39 (2): 90-112 (2006)Security analysis of computing systems from circuit-architectural perspective., and . DSC, page 166-173. IEEE, (2017)Thermal reliability of VCO using InGaP/GaAs HBTs., , and . Microelectron. Reliab., 51 (12): 2147-2152 (2011)ESD Robustness of GaN-on-Si Power Devices under Substrate Biases by means of TLP/VFTLP Tests., , and . IRPS, page 1-5. IEEE, (2020)Leveraging Emerging Technology for Hardware Security - Case Study on Silicon Nanowire FETs and Graphene SymFETs., , , , , and . ATS, page 342-347. IEEE Computer Society, (2014)Logic Obfuscation against IC Reverse Engineering Attacks Using PLGs., and . ICCD, page 341-344. IEEE Computer Society, (2017)