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Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial Applications., , , , , , , and . ATS, page 55-60. IEEE, (2019)Towards approximation during test of Integrated Circuits., , , , , and . DDECS, page 28-33. IEEE, (2017)From onions to broccoli: generalizing Lewis' counterfactual logic.. J. Appl. Non Class. Logics, 17 (2): 213-229 (2007)Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS., , , , , , , and . ITC-Asia, page 73-78. IEEE, (2022)A Low Overhead and Double-Node-Upset Self-Recoverable Latch., , , , , , and . ITC-Asia, page 1-5. IEEE, (2023)Voltage Bootstrapped Schmitt Trigger based Radiation Hardened Latch Design for Reliable Circuits., , , , , and . ACM Great Lakes Symposium on VLSI, page 307-312. ACM, (2021)Two 0.8 V, Highly Reliable RHBD 10T and 12T SRAM Cells for Aerospace Applications., , , , , , , and . ACM Great Lakes Symposium on VLSI, page 261-266. ACM, (2022)A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology., , , , , , , and . ACM Great Lakes Symposium on VLSI, page 255-260. ACM, (2022)Dual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical Applications., , , , , , , and . ISCAS, page 1-5. IEEE, (2020)ProtoTask, New Task Model Simulator., , , and . HCSE, volume 7623 of Lecture Notes in Computer Science, page 323-330. Springer, (2012)