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Disambiguation of "Thirumala, Sandeep Krishna"

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WSe2 based Valley-Coupled-Spintronic Devices for Low Power Non-Volatile Memories.

, , , , , , , and . DRC, page 211-212. IEEE, (2019)

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Sandeep Sadanandan

Sandeep Ameta

Sandeep Kumar

Sandeep Nambiar

Sandeep Pal

 

Other publications of authors with the same name

Computing with ferroelectric FETs: Devices, models, systems, and applications., , , , , , , , , and 9 other author(s). DATE, page 1289-1298. IEEE, (2018)IPS-CiM: Enhancing Energy Efficiency of Intermittently-Powered Systems with Compute-in-Memory., , , and . ICCD, page 368-376. IEEE, (2020)CTCG: Charge-trap based camouflaged gates for reverse engineering prevention., , , , , , and . HOST, page 103-110. IEEE Computer Society, (2018)Valley-Coupled-Spintronic Non-Volatile Memories with Compute-In-Memory Support., , , , , , , , and . CoRR, (2019)Non-Volatile Memory utilizing Reconfigurable Ferroelectric Transistors to enable Differential Read and Energy-Efficient In-Memory Computation., , , and . ISLPED, page 1-6. IEEE, (2019)Polarization-induced Strain-coupled TMD FETs (PS FETs) for Non-Volatile Memory Applications., , , , , and . DRC, page 1-2. IEEE, (2020)A 1.67Tb, 5b/Cell Flash Memory Fabricated in 192-Layer Floating Gate 3D-NAND Technology and Featuring a 23.3Gb/mm2 Bit Density., , , , , , , , , and 34 other author(s). ISSCC, page 400-401. IEEE, (2023)Gate Leakage in Non-Volatile Ferroelectric Transistors: Device-Circuit Implications., and . DRC, page 1-2. IEEE, (2018)Ternary Compute-Enabled Memory using Ferroelectric Transistors for Accelerating Deep Neural Networks., , , and . DATE, page 31-36. IEEE, (2020)WSe2 based Valley-Coupled-Spintronic Devices for Low Power Non-Volatile Memories., , , , , , , and . DRC, page 211-212. IEEE, (2019)