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FPGA Design and Implementation of Accelerated Stereo Matching for Obstacle Detection.

, , , , and . ICEIC, page 1-2. IEEE, (2019)

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Efficient final output feature map processing method supporting real-time object detection and recognition., , , , and . ISOCC, page 324-325. IEEE, (2020)Memory-Centric Architecture of Neural Processing Unit for Edge Device., , , , and . ISOCC, page 240-241. IEEE, (2021)A 4-way pipelined processing architecture for three-step search block-matching motion estimation., and . IEEE Trans. Consumer Electronics, 50 (2): 674-681 (2004)Implementation of a Round Robin Processing Element for Deep Learning Accelerator., , , and . ISOCC, page 302-303. IEEE, (2020)Object Detection Network Robust to Local Illumination Variations., , , and . ISOCC, page 87-88. IEEE, (2021)Hardware implementation of fast traffic sign recognition for intelligent vehicle system., , , and . ISOCC, page 161-162. IEEE, (2016)Robust JPEG2000 Image Transmission over IEEE 802.15.4., , , , , , and . DELTA, page 253-257. IEEE Computer Society, (2008)FPGA Design and Implementation of Accelerated Stereo Matching for Obstacle Detection., , , , and . ICEIC, page 1-2. IEEE, (2019)Lightweight and Energy-Efficient Deep Learning Accelerator for Real-Time Object Detection on Edge Devices., , , , and . Sensors, 23 (3): 1185 (February 2023)Stereo vision-based Collision Avoidance for Unmanned Systems., , and . ISOCC, page 204-205. IEEE, (2018)