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Disambiguation of "Jung, Hae-Kang"

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An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface.

, , , , , , , , and . IEEE J. Solid State Circuits, 49 (11): 2618-2630 (2014)

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Hae-Chang Jung

Min-Jung Kang

Jung-Min Kang

-hae Yu

Hae Namgung

 

Other publications of authors with the same name

13.8 A 1a-nm 1.05V 10.5Gb/s/pin 16Gb LPDDR5 Turbo DRAM with WCK Correction Strategy, a Voltage-Offset-Calibrated Receiver and Parasitic Capacitance Reduction., , , , , , , , , and 20 other author(s). ISSCC, page 246-248. IEEE, (2024)A slew-rate controlled transmitter to compensate for the crosstalk-induced jitter of coupled microstrip lines., , , and . CICC, page 1-4. IEEE, (2010)A 4 Gb/s 3-bit Parallel Transmitter With the Crosstalk-Induced Jitter Compensation Using TX Data Timing Control., , , , , and . IEEE J. Solid State Circuits, 44 (11): 2891-2900 (2009)A 370-fJ/b, 0.0056 mm2/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop., , , , , , , , and . VLSI Circuits, page 94-. IEEE, (2019)A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme, and duty-training circuit for mobile applications., , , , , , , , , and 2 other author(s). VLSIC, page 184-. IEEE, (2015)A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 56 (6): 1886-1896 (2021)A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%-80% Input Duty Cycle for SDRAMs., , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (2): 141-145 (2016)An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface., , , , , , , , and . IEEE J. Solid State Circuits, 49 (11): 2618-2630 (2014)