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Disambiguation of "Park, Hong-June"

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An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface.

, , , , , , , , and . IEEE J. Solid State Circuits, 49 (11): 2618-2630 (2014)

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June Park

Hong-June Kuo

Hong-Yang Park

Hong-Suck Park

Joo-Hong Park

 

Other publications of authors with the same name

A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration., , , , , and . ISSCC, page 112-113. IEEE, (2008)5.5 A quadrature relaxation oscillator with a process-induced frequency-error compensation loop., , , , and . ISSCC, page 94-95. IEEE, (2017)5-Gb/s Peak Detector Using a Current Comparator and a Three-State Charge Pump., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (5): 269-273 (2011)A 10-bit 25-MS/s 1.25-mW Pipelined ADC With a Semidigital Gm-Based Amplifier., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (3): 142-146 (2013)A charge conserving non-quasi-state (NQS) MOSFET model for SPICE transient analysis., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (5): 629-642 (1991)A Coefficient-Error-Robust Feed-Forward Equalizing Transmitter for Eye-Variation and Power Improvement., , , , , and . IEEE J. Solid State Circuits, 51 (8): 1902-1914 (2016)A three-data differential signaling over four conductors with pre-emphasis and equalization: a CMOS current mode implementation., , and . IEEE J. Solid State Circuits, 41 (3): 633-641 (2006)A 5 Gb/s Single-Ended Parallel Receiver With Adaptive Crosstalk-Induced Jitter Cancellation., , , and . IEEE J. Solid State Circuits, 48 (9): 2118-2127 (2013)An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface., , , , , , , and . ISSCC, page 136-138. IEEE, (2012)A 650Mb/s-to-8Gb/s referenceless CDR circuit with automatic acquisition of data rate., , , , , and . ISSCC, page 184-185. IEEE, (2009)