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Towards Gb/s turbo decoding of product code onto an FPGA device.

, , , и . ISCAS, стр. 909-912. IEEE, (2007)

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Nanno Helenus Harmannus Addens

Roland Adden

Gian Antonio d' Addetta

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Petra Adden

 

Другие публикации лиц с тем же именем

A low-complexity soft-decision decoding architecture for the binary extended Golay code., и . ICECS, стр. 705-708. IEEE, (2012)Towards Gb/s turbo decoding of product code onto an FPGA device., , , и . ISCAS, стр. 909-912. IEEE, (2007)Turbo Product Code Decoder Without Interleaving Resource: From Parallelism Exploration to High Efficiency Architecture., , , , и . J. Signal Process. Syst., 64 (1): 17-29 (2011)Turbo-decoder synchronisation procedure: application to the CAS5093 integrated circuit., , и . ICECS, стр. 168-171. IEEE, (1996)Block turbo codes: towards implementation., и . ICECS, стр. 1219-1222. IEEE, (2001)Design and performance of a product code turbo encoding-decoding prototype., , и . Ann. des Télécommunications, 54 (3-4): 214-219 (1999)A Flexible Architecture For Block Turbo Decoders Using BCH Or Reed-Solomon Components Codes., , , и . ISVLSI, стр. 430-431. IEEE Computer Society, (2006)New architecture for high data rate turbo decoding of product codes., , , и . GLOBECOM, стр. 1363-1367. IEEE, (2002)Performance and complexity of block turbo decoder circuits., , и . ICECS, стр. 172-175. IEEE, (1996)Efficient architecture for Reed Solomon block turbo code., , , , и . ISCAS, IEEE, (2006)