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Design and performance of a product code turbo encoding-decoding prototype.

, , and . Ann. des Télécommunications, 54 (3-4): 214-219 (1999)

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A low-complexity soft-decision decoding architecture for the binary extended Golay code., and . ICECS, page 705-708. IEEE, (2012)Towards Gb/s turbo decoding of product code onto an FPGA device., , , and . ISCAS, page 909-912. IEEE, (2007)Turbo Product Code Decoder Without Interleaving Resource: From Parallelism Exploration to High Efficiency Architecture., , , , and . J. Signal Process. Syst., 64 (1): 17-29 (2011)Turbo-decoder synchronisation procedure: application to the CAS5093 integrated circuit., , and . ICECS, page 168-171. IEEE, (1996)New architecture for high data rate turbo decoding of product codes., , , and . GLOBECOM, page 1363-1367. IEEE, (2002)Efficient architecture for Reed Solomon block turbo code., , , , and . ISCAS, IEEE, (2006)A highly parallel Turbo Product Code decoder without interleaving resource., , , , and . SiPS, page 1-6. IEEE, (2008)Performance and complexity of block turbo decoder circuits., , and . ICECS, page 172-175. IEEE, (1996)Block turbo codes: towards implementation., and . ICECS, page 1219-1222. IEEE, (2001)A Flexible Architecture For Block Turbo Decoders Using BCH Or Reed-Solomon Components Codes., , , and . ISVLSI, page 430-431. IEEE Computer Society, (2006)