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Near-Optimal Loop Tiling by Means of Cache Miss Equations and Genetic Algorithms.

J. Abella, A. González, J. Llosa, and X. Vera. ICPP Workshops, page 568-580. IEEE Computer Society, (2002)

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Rafael Eurico Block Siqueira Cavalcanti Veras

Leonardo Verano Gamboa

Galo Vera Chamaza

Antonio Vera

Peter Veranneman-Watervliet

Other publications of authors with the same name

TRAMS Project: Variability and Reliability of SRAM Memories in sub-22 nm Bulk-CMOS Technologies.R. Canal, A. Rubio, A. Asenov, A. Brown, M. Miranda, P. Zuber, A. González, and X. Vera. FET, volume 7 of Procedia Computer Science, page 148-149. Elsevier, (2011)A Fast and Accurate Approach to Analyze Cache Memory Behavior (Research Note).X. Vera, J. Llosa, A. González, and N. Bermudo. Euro-Par, volume 1900 of Lecture Notes in Computer Science, page 194-198. Springer, (2000)Low Vccmin fault-tolerant cache with highly predictable performance.J. Abella, J. Carretero, P. Chaparro, X. Vera, and A. González. MICRO, page 111-121. ACM, (2009)VCTA: A Via-Configurable Transistor Array regular fabric.M. Pons, F. Moll, A. Rubio, J. Abella, X. Vera, and A. González. VLSI-SoC, page 335-340. IEEE, (2010)On-line Failure Detection in Memory Order Buffers.J. Carretero, X. Vera, P. Chaparro, and J. Abella. ITC, page 1-10. IEEE Computer Society, (2008)Control-Flow Recovery Validation Using Microarchitectural Invariants.J. Carretero, J. Abella, X. Vera, and P. Chaparro. DFT, page 209-216. IEEE Computer Society, (2011)Online error detection and correction of erratic bits in register files.X. Vera, J. Abella, J. Carretero, P. Chaparro, and A. González. IOLTS, page 81-86. IEEE Computer Society, (2009)On-Line Failure Detection and Confinement in Caches.J. Abella, P. Chaparro, X. Vera, J. Carretero, and A. González. IOLTS, page 3-9. IEEE Computer Society, (2008)Issue system protection mechanisms.P. Chaparro, J. Abella, J. Carretero, and X. Vera. ICCD, page 599-604. IEEE Computer Society, (2008)Architectures for online error detection and recovery in multicore processors.D. Gizopoulos, M. Psarakis, S. Adve, P. Ramachandran, S. Hari, D. Sorin, A. Meixner, A. Biswas, and X. Vera. DATE, page 533-538. IEEE, (2011)

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Disambiguation of "Vera, Xavier"

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Near-Optimal Loop Tiling by Means of Cache Miss Equations and Genetic Algorithms.

Please choose a person to relate this publication to

Rafael Eurico Block Siqueira Cavalcanti Veras

Leonardo Verano Gamboa

Galo Vera Chamaza

Antonio Vera

Peter Veranneman-Watervliet

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Vera, Xavier"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Near-Optimal Loop Tiling by Means of Cache Miss Equations and Genetic Algorithms.

Please choose a person to relate this publication to

Rafael Eurico Block Siqueira Cavalcanti Veras

Leonardo Verano Gamboa

Galo Vera Chamaza

Antonio Vera

Peter Veranneman-Watervliet

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
Harvard
MSOffice XML

Near-Optimal Loop Tiling by Means of Cache Miss Equations and Genetic Algorithms.