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A Dynamic Partial Reconfigurable CGRA Framework for Multi-Kernel Applications.

, , , , , and . ICFPT, page 298-299. IEEE, (2023)

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A High-performance Open-channel Open-way NAND Flash Controller Architecture., , and . FPL, page 91-98. IEEE, (2021)An Automatic Optimization Method of Combinational Logic Loops in CGRA., , , and . ASICON, page 1-4. IEEE, (2023)High Throughput and Low Latency Multi-Version Management Key-Value Storage Accelerator., , , , and . FPT, page 290-291. IEEE, (2020)TRAM: An Open-Source Template-based Reconfigurable Architecture Modeling Framework., , , , and . FPL, page 61-69. IEEE, (2022)PRAD: A Bayesian Optimization-based DSE Framework for Parameterized Reconfigurable Architecture Design., , , , , , , and . FCCM, page 226. IEEE, (2023)E2-ACE: An Energy-Efficient Reconfigurable Crypto-Accelerator with Agile End-to-End Toolchain., , , , , and . ICFPT, page 296-297. IEEE, (2023)An Agile Deploying Approach for Large-Scale Workloads on CGRA-CPU Architecture., , , , , , and . DATE, page 1-6. IEEE, (2024)High-Throughput and Low-Latency Distributed Management Proxy for Key-Value Store Over 100Gbps Ethernet on FPGA., , , and . FPT, page 224-230. IEEE, (2019)A Low-Latency Multi-Version Key-Value Store Using B-Tree on an FPGA-CPU Platform., , , , , , , , , and 1 other author(s). FPL, page 321-325. IEEE, (2019)UPTRA: An Ultra-Parameterized Temporal CGRA Modeling and Optimization., , , , , and . FCCM, page 208. IEEE, (2023)