Author of the publication

Irredundant sequential machines via optimal logic synthesis.

, , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 9 (1): 8-18 (1990)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

On the Verification of Sequential Machines at Differing Levels of Abstraction., , and . DAC, page 271-276. IEEE Computer Society Press / ACM, (1987)Experiments on the synthesis and testability of non-scan finite state machines., , and . EURO-DAC, page 537-542. IEEE Computer Society Press, (1992)Integration of retiming with architectural floorplanning., , , and . Integr., 29 (1): 25-43 (2000)The exploitation of latency and multirate behavior using nonlinear relaxation for circuit simulation., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 8 (12): 1286-1298 (1989)Decomposition and factorization of sequential finite state machines., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 8 (11): 1206-1217 (1989)Test generation for sequential circuits., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 7 (10): 1081-1093 (1988)A synthesis and optimization procedure for fully and easily testable sequential machines., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 8 (10): 1100-1107 (1989)System-level design: orthogonalization of concerns andplatform-based design., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (12): 1523-1543 (2000)MUSE: a multilevel symbolic encoding algorithm for state assignment., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (1): 28-38 (1991)Highlights of VLSI Research at Berkeley., , and . FJCC, page 894-897. IEEE Computer Society, (1986)