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Disambiguation of "Ling, Ming"

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Vina-FPGA: A Hardware-Accelerated Molecular Docking Tool With Fixed-Point Quantization and Low-Level Parallelism.

, , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 31 (4): 484-497 (April 2023)

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Dchi-ling Ling

Jorge Mínguez

Karl Minga

Bernhard Mingers

Roland Minges

 

Other publications of authors with the same name

A novel energy-oriented reconfigurable on-chip unified memory architecture based on Cache Behavior Phase Graph., , , , and . ASICON, page 1-5. IEEE, (2013)An artificial neural network model of LRU-cache misses on out-of-order embedded processors., , , and . Microprocess. Microsystems, (2017)TYMER: A Yield-based Performance Model for Timing-speculation SRAM., , , , , and . DAC, page 1-6. IEEE, (2020)A Cross-Layer Power and Timing Evaluation Method for Wide Voltage Scaling., , , , and . DAC, page 1-6. IEEE, (2020)Dual fluoroscopic imaging and CT-based finite element modelling to estimate forces and stresses of grafts in anatomical single-bundle ACL reconstruction with different femoral tunnels., , , , , , and . Int. J. Comput. Assist. Radiol. Surg., 16 (3): 495-504 (2021)A Novel Delay Calibration Method Considering Interaction between Cells and Wires., , , , , , and . DATE, page 1-6. IEEE, (2023)A New Process Framework for Managing the Fuzzy Front End of New Healthcare Device Development., , , and . HCI (24), volume 14034 of Lecture Notes in Computer Science, page 480-491. Springer, (2023)Analytical Modeling the Multi-Core Shared Cache Behavior With Considerations of Data-Sharing and Coherence., , , and . IEEE Access, (2021)A Timing Yield Model for SRAM Cells at Sub/Near-Threshold Voltages Based on a Compact Drain Current Model., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (4): 1223-1234 (April 2023)A mechanistic model of memory level parallelism fed with cache miss rates., , , and . PACRIM, page 1-6. IEEE, (2017)