( en | de | ru )

 

Disambiguation of "Sakurai, Takayasu"

Author of the publication

copydeleteadd this publication to your clipboard
Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature.

, , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 59-II (12): 918-921 (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Yoriko Sakurai

Kaneaki Sakurai

Takayasu Shimizu

Miriam Takayasu

 

Other publications of authors with the same name

High-Speed Circuit Design with Scaled-Down MOSFET's and Low Supply Voltage.. ISCAS, page 1487-1490. IEEE, (1993)A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping., , , and . ISSCC, page 358-608. IEEE, (2007)Reducing IR drop in 3D integration to less than 1/4 using Buck Converter on Top die (BCT) scheme., , , , , , , and . ISQED, page 210-215. IEEE, (2013)A 1.8V 30nJ adaptive program-voltage (20V) generator for 3D-integrated NAND flash SSD., , , , , , and . ISSCC, page 238-239. IEEE, (2009)A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking., , , , , , , and . ISSCC, page 244-245. IEEE, (2009)Ambient electronics and ultra-low power LSI design.. VLSI-DAT, page 1-31. IEEE, (2012)0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS., , , , , , , and . CICC, page 1-4. IEEE, (2010)An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOS., , , and . ASP-DAC, page 109-110. IEEE, (2011)A low voltage buck DC-DC converter using on-chip gate boost technique in 40nm CMOS., , , , , , , and . ASP-DAC, page 109-110. IEEE, (2013)Digital Active Gate Drive with Optimal Switching Patterns to Adapt to Sinusoidal Output Current in a Full Bridge Inverter Circuit., , , , , , , and . IECON, page 1684-1689. IEEE, (2019)