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A 1.4Mb 40-nm embedded ReRAM macro with 0.07um2 bit cell, 2.7mA/100MHz low-power read and hybrid write verify for high endurance application.

C. Lee, H. Lin, C. Lien, Y. Chih, and T. Chang. A-SSCC, page 9-12. IEEE, (2017)

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Lena Jarnot

Anwar Hasan Jarndal

Lin Lin

Other publications of authors with the same name

Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with Hybrid-Resistance Reference, Sub-μA Sensing Resolution, and 17.5NS Read Access Time.Y. Shih, C. Lee, Y. Chang, P. Lee, H. Lin, Y. Chen, K. Lin, T. Yeh, H. Yu, H. Chuang and 2 other author(s). VLSI Circuits, page 79-80. IEEE, (2018)13.3 A 22nm 32Mb Embedded STT-MRAM with 10ns Read Speed, 1M Cycle Write Endurance, 10 Years Retention at 150°C and High Immunity to Magnetic Field Interference.Y. Chih, Y. Shih, C. Lee, Y. Chang, P. Lee, H. Lin, Y. Chen, C. Lo, M. Shih, K. Shen and 2 other author(s). ISSCC, page 222-224. IEEE, (2020)A Two-Write and Two-Read Multi-Port SRAM with Shared Write Bit-Line Scheme and Selective Read Path for Low Power Operation.D. Wang, H. Lin, and W. Hwang. J. Low Power Electron., 9 (1): 9-22 (2013)A 1.4Mb 40-nm embedded ReRAM macro with 0.07um2 bit cell, 2.7mA/100MHz low-power read and hybrid write verify for high endurance application.C. Lee, H. Lin, C. Lien, Y. Chih, and T. Chang. A-SSCC, page 9-12. IEEE, (2017)A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity.P. Lee, C. Lee, Y. Shih, H. Lin, Y. Chang, C. Lu, Y. Chen, C. Lo, C. Chen, C. Kuo and 8 other author(s). ISSCC, page 494-495. IEEE, (2023)

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Disambiguation of "Lin, Hon-Jarn"

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A 1.4Mb 40-nm embedded ReRAM macro with 0.07um2 bit cell, 2.7mA/100MHz low-power read and hybrid write verify for high endurance application.

Please choose a person to relate this publication to

Lena Jarnot

Anwar Hasan Jarndal

Lin Lin

Lin Lin

Lin Lin

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Lin, Hon-Jarn"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 1.4Mb 40-nm embedded ReRAM macro with 0.07um2 bit cell, 2.7mA/100MHz low-power read and hybrid write verify for high endurance application.

Please choose a person to relate this publication to

Lena Jarnot

Anwar Hasan Jarndal

Lin Lin

Lin Lin

Lin Lin

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 1.4Mb 40-nm embedded ReRAM macro with 0.07um2 bit cell, 2.7mA/100MHz low-power read and hybrid write verify for high endurance application.