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A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity.

P. Lee, C. Lee, Y. Shih, H. Lin, Y. Chang, C. Lu, Y. Chen, C. Lo, C. Chen, C. Kuo, T. Chou, C. Wang, J. Wu, R. Wang, H. Chuang, Y. Wang, Y. Chih, and T. Chang. ISSCC, page 494-495. IEEE, (2023)

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Pu Chen

Jianfeng Pu

Jielin Pu

Lingling Pu

Jianjun Pu

Other publications of authors with the same name

An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications.Y. Chih, P. Lee, H. Fujiwara, Y. Shih, C. Lee, R. Naous, Y. Chen, C. Lo, C. Lu, H. Mori and 10 other author(s). ISSCC, page 252-254. IEEE, (2021)13.3 A 22nm 32Mb Embedded STT-MRAM with 10ns Read Speed, 1M Cycle Write Endurance, 10 Years Retention at 150°C and High Immunity to Magnetic Field Interference.Y. Chih, Y. Shih, C. Lee, Y. Chang, P. Lee, H. Lin, Y. Chen, C. Lo, M. Shih, K. Shen and 2 other author(s). ISSCC, page 222-224. IEEE, (2020)CILP: An Arbitrary-bit Precision All-digital Compute-in-memory Solver for Integer Linear Programming Problems.M. Yang, Y. Wang, S. Xie, C. Lo, M. Wang, S. Oruganti, R. Sehgal, and J. Kulkarni. CICC, page 1-2. IEEE, (2024)30.6 Vecim: A 289.13GOPS/W RISC-V Vector Co-Processor with Compute-in-Memory Vector Register File for Efficient High-Performance Computing.Y. Wang, M. Yang, C. Lo, and J. Kulkarni. ISSCC, page 492-494. IEEE, (2024)7.4 A 256b-wordlength ReRAM-based TCAM with 1ns search-time and 14× improvement in wordlength-energyefficiency-density product using 2.5T1R cell.C. Lin, J. Hung, W. Lin, C. Lo, Y. Chiang, H. Tsai, G. Yang, Y. King, C. Lin, T. Chen and 1 other author(s). ISSCC, page 136-137. IEEE, (2016)4.7 A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic.Y. Liu, Z. Wang, A. Lee, F. Su, C. Lo, Z. Yuan, C. Lin, Q. Wei, Y. Wang, Y. King and 5 other author(s). ISSCC, page 84-86. IEEE, (2016)A 22nm 4Mb STT-MRAM Data-Encrypted Near-Memory Computation Macro with a 192GB/s Read-and-Decryption Bandwidth and 25.1-55.1TOPS/W 8b MAC for AI Operations.Y. Chiu, C. Yang, S. Teng, H. Huang, F. Chang, Y. Wu, Y. Chien, F. Hsieh, C. Li, G. Lin and 11 other author(s). ISSCC, page 178-180. IEEE, (2022)A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity.P. Lee, C. Lee, Y. Shih, H. Lin, Y. Chang, C. Lu, Y. Chen, C. Lo, C. Chen, C. Kuo and 8 other author(s). ISSCC, page 494-495. IEEE, (2023)A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors.A. Lee, C. Lo, C. Lin, W. Chen, K. Hsu, Z. Wang, F. Su, Z. Yuan, Q. Wei, Y. King and 8 other author(s). IEEE J. Solid State Circuits, 52 (8): 2194-2207 (2017)A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed.Z. Wang, Y. Liu, A. Lee, F. Su, C. Lo, Z. Yuan, J. Li, C. Lin, W. Chen, H. Chiu and 7 other author(s). IEEE J. Solid State Circuits, 52 (10): 2769-2785 (2017)

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Disambiguation of "Lo, Chieh-Pu"

Please choose a person to relate this publication to

Pu Chen

Jianfeng Pu

Jielin Pu

Lingling Pu

Jianjun Pu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Lo, Chieh-Pu"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity.

Please choose a person to relate this publication to

Pu Chen

Jianfeng Pu

Jielin Pu

Lingling Pu

Jianjun Pu

Other publications of authors with the same name

Disambiguation