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Disambiguation of "Miura, Yukiya"

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On-Chip Delay Measurement for Degradation Detection And Its Evaluation under Accelerated Life Test.

, , , , , , and . IOLTS, page 1-6. IEEE, (2020)

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Naotomo Miura

Kota Miura

Yuzuru Miura

 

Other publications of authors with the same name

Development of FF Circuits for Measures Against Power Supply Noise., , and . IOLTS, page 48-51. IEEE, (2019)Dual Edge Triggered Flip-Flops for Noise Blocking and Application to Signal Delay Detection., and . Asian Test Symposium, page 119-124. IEEE Computer Society, (2012)Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits., , and . Asian Test Symposium, page 120-124. IEEE Computer Society, (2000)Current Testable Design of Resistor String DACs., , , , and . ATS, page 399-403. IEEE, (2007)Hybrid Rocket Engine Design Using Pairwise Ranking Surrogate-assisted Differential Evolution., , , and . GECCO Companion, page 1956-1962. ACM, (2023)Built - in concurrent testing for semiconductor random access memories by concurrently testing cells on a word-line., , and . Syst. Comput. Jpn., 19 (6): 50-62 (1988)A built-in test for functional testing in semiconductor random access memory., , and . Syst. Comput. Jpn., 18 (9): 64-73 (1987)An On-Chip Digital Environment Monitor for Field Test., , , and . ATS, page 254-257. IEEE Computer Society, (2014)Real-Time Current Testing for A/D Converters.. IEEE Des. Test Comput., 13 (2): 34-41 (1996)A noise-tolerant master-slave flip-flop., and . IOLTS, page 55-61. IEEE, (2014)