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Performance linked dynamic cache tuning: A static energy reduction approach in tiled CMPs., и . Microprocess. Microsystems, (2017)Reinforcement Learning Based Refresh Optimized Volatile STT-RAM Cache., и . ISVLSI, стр. 222-227. IEEE, (2020)Restricting writes for energy-efficient hybrid cache in multi-core architectures., и . VLSI-SoC, стр. 1-6. IEEE, (2016)Random-LRU: A Replacement Policy for Chip Multiprocessors., , , и . VDAT, том 382 из Communications in Computer and Information Science, стр. 204-213. Springer, (2013)Improving Static Power Efficiency via Placement of Network Demultiplexer over Control Plane of Router in Multi-NoCs., , , и . DAC, стр. 225. ACM, (2019)Modelling Latency-Insensitive Systems in CSP.. ACSD, стр. 231-232. IEEE Computer Society, (2007)AGRAS: Aging and memory request rate aware scheduler for PCM memories., и . ISQED, стр. 1-8. IEEE, (2023)DAMUS: Dynamic Allocation based on Write Frequency in MUlti-Retention STT-RAM based Last Level Caches., , , , и . ISQED, стр. 469-475. IEEE, (2021)SRS-Mig: Selection and Run-time Scheduling of page Migration for improved response time in hybrid PCM-DRAM memories., , , и . ACM Great Lakes Symposium on VLSI, стр. 217-222. ACM, (2022)DidaSel: dirty data based selection of VC for effective utilization of NVM buffers in on-chip interconnects., , и . ISLPED, стр. 151-156. ACM, (2020)