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Performance linked dynamic cache tuning: A static energy reduction approach in tiled CMPs., и . Microprocess. Microsystems, (2017)WaFFLe: Gated Cache-Ways with Per-Core Fine-Grained DVFS for Reduced On-Chip Temperature and Leakage Consumption., и . ACM Trans. Archit. Code Optim., 18 (4): 55:1-55:25 (2021)RePAiR: A Strategy for Reducing Peak Temperature while Maximising Accuracy of Approximate Real-Time Computing: Work-in-Progress., , , и . CODES+ISSS, стр. 8-10. IEEE, (2020)TEEMO: Temperature Aware Energy Efficient Multi-Retention STT-RAM Cache Architecture., , и . IPDPS, стр. 852-864. IEEE, (2024)TREAFET: Temperature-Aware Real-Time Task Scheduling for FinFET based Multicores., , и . ACM Trans. Embed. Comput. Syst., 23 (4): 61:1-61:31 (июля 2024)A New Recursive Partitioning Multicast Routing Algorithm for 3D Network-on-Chip., , и . VDAT, стр. 1-6. IEEE, (2014)Power aware cache miss reduction by energy efficient victim retention., , и . VDAT, стр. 1-6. IEEE Computer Society, (2015)NTHPC: Embracing Near-Threshold Operation for High Performance Multi-core Systems., , и . SAMOS, том 14385 из Lecture Notes in Computer Science, стр. 33-42. Springer, (2023)ABACa: Access Based Allocation on Set Wise Multi-Retention in STT-RAM Last Level Cache., и . ASAP, стр. 171-174. IEEE, (2021)Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR)., , и . DAC, стр. 1-6. IEEE, (2023)