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Fast and accurate estimation of nano-scaled SRAM read failure probability using critical point sampling.

, , , , and . CICC, page 439-442. IEEE, (2005)

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Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations., , and . ICCAD, page 736-741. IEEE Computer Society, (2005)Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement., , , , and . DAC, page 358-363. IEEE, (2007)Characterization of NBTI induced temporal performance degradation in nano-scale SRAM array using IDDQ., , and . ITC, page 1-10. IEEE Computer Society, (2007)Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop., , and . DAC, page 934-939. IEEE, (2007)Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI., , , and . ICCD, page 216-221. IEEE, (2006)Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations., , , , and . ISLPED, page 14-19. ACM, (2005)Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance., , , and . ICCAD, page 730-734. IEEE Computer Society, (2007)Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling., , , and . IET Circuits Devices Syst., 4 (6): 469-478 (2010)Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (1): 46-59 (2009)High Performance and Low Power Electronics on Flexible Substrate., , , and . DAC, page 274-275. IEEE, (2007)