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Disambiguation of "Cho, Hyunyoon"

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Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM.

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Miyeon Cho

Photooxygenierung in Mikroemulsionen und mit dualen Photokatalysatoren. Uni Köln, (2009)

Seongdon Cho

Myunghun Cho

Soon Cho

Yongsun Cho

 

Other publications of authors with the same name

A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics., , , , , , , , , and 4 other author(s). ESSCIRC, page 463-466. IEEE, (2021)A 40-Gb/s/pin Low-Voltage POD Single-Ended PAM-4 Transceiver with Timing Calibrated Reset-less Slicer and Bidirectional T-Coil for GDDR7 Application., , , , , , , , , and 13 other author(s). VLSI Technology and Circuits, page 148-149. IEEE, (2022)Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices., , , , , , , , , and 2 other author(s). HPCA, page 61-72. IEEE Computer Society, (2017)A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power., , , , , , , , , and 20 other author(s). ISSCC, page 378-380. IEEE, (2019)A 60-Gb/s/pin single-ended PAM-4 transmitter with timing skew training and low power data encoding in mimicked 10nm class DRAM process., , , , , , , , , and 18 other author(s). CICC, page 1-2. IEEE, (2022)A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme., , , , , , , , , and 9 other author(s). ISSCC, page 44-46. IEEE, (2012)A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking., , , , , , , , , and 13 other author(s). ISSCC, page 496-498. IEEE, (2011)Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM., , , , , , , , , and 25 other author(s). A-SSCC, page 153-156. IEEE, (2017)22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process., , , , , , , , , and 29 other author(s). ISSCC, page 382-384. IEEE, (2020)A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE., , , , , , , , , and . A-SSCC, page 1-3. IEEE, (2021)