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Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond.

K. Ishibashi, T. Fujimoto, T. Yamashita, H. Okada, Y. Arima, Y. Hashimoto, K. Sakata, I. Minematsu, Y. Itoh, H. Toda, M. Ichihashi, Y. Komatsu, M. Hagiwara, and T. Tsukada. IEICE Trans. Electron., 89-C (3): 250-262 (2006)

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Guido Komatsu

Eiichiro Komatsu

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Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond.K. Ishibashi, T. Fujimoto, T. Yamashita, H. Okada, Y. Arima, Y. Hashimoto, K. Sakata, I. Minematsu, Y. Itoh, H. Toda and 4 other author(s). IEICE Trans. Electron., 89-C (3): 250-262 (2006)Investigation of the Failure Mechanism of InGaAs-pHEMT under High Temperature Operating Life Tests.Y. Tateno, K. Nakata, A. Oya, K. Matsuda, Y. Komatsu, S. Osada, M. Hirata, S. Ishiyama, T. Yoda, A. Nitta and 1 other author(s). IRPS, page 1-4. IEEE, (2021)A soft-error hardened latch scheme for SoC in a 90 nm technology and beyond.Y. Komatsu, Y. Arima, T. Fujimoto, T. Yamashita, and K. Ishibashi. CICC, page 329-332. IEEE, (2004)A 0.25-27Gb/s Wideband PAM4/NRZ Transceiver with Adaptive Power CDR for 8K System.Y. Komatsu, A. Shinmyo, M. Funabashi, S. Kato, K. Hatooka, K. Tanaka, M. Fujita, and K. Fukuda. A-SSCC, page 63-66. IEEE, (2018)Substrate-noise and random-fluctuations reduction with self-adjusted forward body bias.Y. Komatsu, K. Ishibashi, M. Yamamoto, T. Tsukada, K. Shimazaki, M. Fukazawa, and M. Nagata. CICC, page 35-38. IEEE, (2005)Soft Error Hardened Latch Scheme with Forward Body Bias in a 90-nm Technology and Beyond.Y. Komatsu, Y. Arima, and K. Ishibashi. IEICE Trans. Electron., 89-C (3): 384-391 (2006)

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Disambiguation of "Komatsu, Yoshihide"

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Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond.

Please choose a person to relate this publication to

Guido Komatsu

Eiichiro Komatsu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Komatsu, Yoshihide"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond.

Please choose a person to relate this publication to

Guido Komatsu

Eiichiro Komatsu

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond.