Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond.

K. Ishibashi, T. Fujimoto, T. Yamashita, H. Okada, Y. Arima, Y. Hashimoto, K. Sakata, I. Minematsu, Y. Itoh, H. Toda, M. Ichihashi, Y. Komatsu, M. Hagiwara, and T. Tsukada. IEICE Trans. Electron., 89-C (3): 250-262 (2006)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Yasuhisa Ichihashi

Motoi Masubuchi

Other publications of authors with the same name

How to Cope with Slow Transistors in the Top-tier of Monolithic 3D ICs: Design Studies and CAD Solutions.S. Samal, D. Nayak, M. Ichihashi, S. Banna, and S. Lim. ISLPED, page 320-325. ACM, (2016)Tier partitioning strategy to mitigate BEOL degradation and cost issues in monolithic 3D ICs.S. Samal, D. Nayak, M. Ichihashi, S. Banna, and S. Lim. ICCAD, page 129. ACM, (2016)On the Design of Ultra-High Density 14nm Finfet Based Transistor-Level Monolithic 3D ICs.J. Shi, D. Nayak, M. Ichihashi, S. Banna, and C. Moritz. ISVLSI, page 449-454. IEEE Computer Society, (2016)Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond.K. Ishibashi, T. Fujimoto, T. Yamashita, H. Okada, Y. Arima, Y. Hashimoto, K. Sakata, I. Minematsu, Y. Itoh, H. Toda and 4 other author(s). IEICE Trans. Electron., 89-C (3): 250-262 (2006)Performance Boost Scheme with Activated Dummy Fin in 12-nm FinFET Technology for High-Performance Logic Application.M. Ichihashi, J. Zeng, Y. Woo, X. Zhu, C. Wang, and J. Mazza. ISQED, page 196. IEEE, (2020)10T Differential-Signal SRAM Design in a L4-NM FinFET Technology for High-Speed Application.M. Ichihashi, Y. Woo, M. Karim, V. Joshi, and D. Burnett. SoCC, page 322-325. IEEE, (2018)Performance Measurement and Improvement of Asymmetric Three-Tr. Cell (ATC) DRAM toward 0.3V Memory Array Operation.M. Ichihashi, and H. Toda. VLSI Design, page 487-490. IEEE Computer Society, (2006)An On-Chip Multi-mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-power Domain SoC Using a 65-nm Standard CMOS Logic Process.M. Ichihashi, H. Lhermet, E. Beigné, F. Rothan, M. Belleville, and A. Amara. PATMOS, volume 5953 of Lecture Notes in Computer Science, page 336-346. Springer, (2009)

BibSonomy

Disambiguation of "Ichihashi, Motoi"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond.

Please choose a person to relate this publication to

Yasuhisa Ichihashi

Motoi Masubuchi

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Ichihashi, Motoi"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond.

Please choose a person to relate this publication to

Yasuhisa Ichihashi

Motoi Masubuchi

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond.