( en | de | ru )

 

Disambiguation of "Su, Alan P."

Author of the publication

copydeleteadd this publication to your clipboard
Transaction Level Modeling and Design Space Exploration for SOC Test Architectures.

, , , and . Asian Test Symposium, page 200-205. IEEE Computer Society, (2009)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Maia Alandjiyska

Safwat Alani

Yilmaz Alan

Viola Alanku

Bertold Aland

 

Other publications of authors with the same name

A low power synthesis flow for multi-rate systems., , and . VLSI-DAT, page 1-4. IEEE, (2017)A Hybrid Multicast Routing Approach with Enhanced Methods for Mesh-Based Networks-on-Chip., , and . IEEE Trans. Computers, 67 (9): 1231-1245 (2018)Transaction Level Modeling and Design Space Exploration for SOC Test Architectures., , , and . Asian Test Symposium, page 200-205. IEEE Computer Society, (2009)Buffer size minimization method considering mix-clock domains and discontinuous data access., , , and . APCCAS, page 380-383. IEEE, (2012)Applying ESL in A Dual-Core SoC Platform Designing., and . SoCC, page 171-174. IEEE, (2006)A practice of ESL verification methodology from SystemC to FPGA: using EPC class-1 generation-2 RFID tag design as an example., , , , and . ASP-DAC, page 821-824. IEEE, (2010)Flow Maximization for NoC Routing Algorithms., , , , and . ISVLSI, page 335-340. IEEE Computer Society, (2008)A low-cost SOC debug platform based on on-chip test architectures., , and . SoCC, page 161-164. IEEE, (2009)Fluidity concept for NoC: A congestion avoidance and relief routing scheme., , , , and . SoCC, page 65-70. IEEE, (2008)An architectural co-synthesis algorithm for energy-aware network-on-chip design., , , , and . SAC, page 680-684. ACM, (2007)