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Filtering Directory Lookups in CMPs with Write-Through Caches.

, , , and . Euro-Par (1), volume 6852 of Lecture Notes in Computer Science, page 269-281. Springer, (2011)

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A performance evaluation of the multiple bus network for multiprocessor systems., , , , and . SIGMETRICS, page 200-206. ACM, (1983)A Mechanism for Verifying Data Speculation., , and . Euro-Par, volume 3149 of Lecture Notes in Computer Science, page 525-534. Springer, (2004)Exploiting reuse locality on inclusive shared last-level caches., , , and . ACM Trans. Archit. Code Optim., 9 (4): 38:1-38:19 (2013)Increasing the Effective Bandwidth of Complex Memory Systems in Multivector Processors., and . SC, page 26. IEEE Computer Society, (1996)Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors., , , , , and . HPCA, page 191-202. IEEE Computer Society, (2003)An Enhancement for a Scheduling Logic Pipelined over two Cycles ., , , and . ICCD, page 203-209. IEEE, (2006)Counteracting Bank Misprediction in Sliced First-Level Caches., , , and . Euro-Par, volume 2790 of Lecture Notes in Computer Science, page 586-596. Springer, (2003)Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation., , , , , and . IEEE PACT, page 170-181. IEEE Computer Society, (2003)Loop bounds computation for multilevel tiling., , and . PDP, page 445-452. IEEE Computer Society, (1998)Store Buffer Design for Multibanked Data Caches., , , and . IEEE Trans. Computers, 58 (10): 1307-1320 (2009)