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Dual-Line-Systolic Array for High Performance CNN Accelerator.

P. Xue, L. Pan, L. Sun, and M. Huang. FCCM, page 1. IEEE, (2022)

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Haishi Huang

Zhida Huang

Ying Huang

Feiqing Huang

Haowei Huang

Other publications of authors with the same name

Multi-bit-width CNN Accelerator with Systolic-in-Systolic Dataflow and Single DSP Multiple Multiplication Scheme.M. Huang, Y. Liu, S. Huang, K. Li, Q. Wu, and H. Yu. FPGA, page 229. ACM, (2023)Group Vectored Absolute-Value-Subtraction Cell Array for the Efficient Acceleration of AdderNet.J. Chen, W. Hu, W. Ma, Z. Zhang, and M. Huang. AICAS, page 1-5. IEEE, (2023)A 29.12 TOPS/W and 1.13 TOPS/mm2 NAS-Optimized Mixed-Precision DNN Accelerator with Vector Split- and-Combination Systolic in 28nm CMOS.K. Li, H. Huang, M. Huang, C. Ding, L. Lin, L. Ni, and H. Yu. CICC, page 1-2. IEEE, (2024)An Energy-Efficient Mixed-Bit CNN Accelerator With Column Parallel Readout for ReRAM-Based In-Memory Computing.D. Liu, H. Zhou, W. Mao, J. Liu, Y. Han, C. Man, Q. Wu, Z. Guo, M. Huang, S. Luo and 3 other author(s). IEEE J. Emerg. Sel. Topics Circuits Syst., 12 (4): 821-834 (2022)Hardware-Friendly Stochastic and Adaptive Learning in Memristor Convolutional Neural Networks.W. Zhang, L. Pan, X. Yan, G. Zhao, H. Chen, X. Wang, B. Tay, G. Zhong, J. Li, and M. Huang. Adv. Intell. Syst., 3 (9): 2100041 (2021)A Precision-Scalable Energy-Efficient Bit-Split-and-Combination Vector Systolic Accelerator for NAS-Optimized DNNs on Edge.K. Li, J. Zhou, Y. Wang, J. Luo, Z. Yang, S. Yang, W. Mao, M. Huang, and H. Yu. DATE, page 730-735. IEEE, (2022)High performance transistors based on two dimensional materials.M. Huang, X. Xiong, T. Li, and Y. Wu. ASICON, page 1053-1056. IEEE, (2017)Dual-Line-Systolic Array for High Performance CNN Accelerator.P. Xue, L. Pan, L. Sun, and M. Huang. FCCM, page 1. IEEE, (2022)A General-Purpose and Configurable Planar Data Processor for Energy-Efficient Pooling Computation.L. Pan, P. Xue, H. Li, L. Sun, and M. Huang. AICAS, page 33-36. IEEE, (2022)A High Throughput Multi-bit-width 3D Systolic Accelerator for NAS Optimized Deep Neural Networks on FPGA.M. Huang, Y. Liu, Q. Cheng, S. Yang, K. Li, J. Luo, Z. Yang, Q. Li, H. Yu, and C. Man. FPGA, page 50. ACM, (2022)

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Disambiguation of "Huang, Mingqiang"

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Dual-Line-Systolic Array for High Performance CNN Accelerator.

Please choose a person to relate this publication to

Haishi Huang

Zhida Huang

Ying Huang

Feiqing Huang

Haowei Huang

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Huang, Mingqiang"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Dual-Line-Systolic Array for High Performance CNN Accelerator.

Please choose a person to relate this publication to

Haishi Huang

Zhida Huang

Ying Huang

Feiqing Huang

Haowei Huang

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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Dual-Line-Systolic Array for High Performance CNN Accelerator.