Author of the publication

Reliability Issues in Deep Deep Submicron Technologies: Time-Dependent Variability and its Impact on Embedded System Design.

, , , , and . VLSI-SoC (Selected Papers), volume 249 of IFIP, page 119-141. Springer, (2006)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A low leakage 500MHz 2T embedded dynamic memory with integrated semi-transparent refresh., , and . ESSCIRC, page 523-526. IEEE, (2011)Variation-resilient sub-threshold circuit solutions for ultra-low-power Digital Signal Processors with 10MHz clock frequency., and . ESSCIRC, page 474-477. IEEE, (2012)Design and Synthesis of Pareto Buffers Offering Large Range Runtime Energy/Delay Tradeoffs Via Combined Buffer Size and Supply Voltage Tuning., , , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (1): 117-127 (2009)A 16nm 128kB high-density fully digital In Memory Compute macro with reverse SRAM pre-charge achieving 0.36TOPs/mm2, 256kB/mm2 and 23. 8TOPs/W., , , and . ESSCIRC, page 409-412. IEEE, (2023)Dual-Input Pseudo-CMOS Logic for Digital Applications on Flexible Substrates., , and . ESSCIRC, page 255-258. IEEE, (2021)A flexible, ultra-low power 35pJ/pulse digital back-end for a QAC UWB receiver., and . ESSCIRC, page 236-239. IEEE, (2007)A dual port dual width 90nm SRAM with guaranteed data retention at minimal standby supply voltage., and . ESSCIRC, page 290-293. IEEE, (2008)30.1 8b Thin-film microprocessor using a hybrid oxide-organic complementary technology with inkjet-printed P2ROM memory., , , , , , , , , and 7 other author(s). ISSCC, page 486-487. IEEE, (2014)Energy and side-channel security evaluation of near-threshold cryptographic circuits in 28nm FD-SOI technology., , , , , , , , and . CF, page 258-262. ACM, (2022)A Differential Transmission Gate Design Flow for Minimum Energy Sub-10-pJ/Cycle ARM Cortex-M0 MCUs., and . IEEE J. Solid State Circuits, 52 (7): 1904-1914 (2017)