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Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (5): 726-739 (2015)A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier., , , , , , and . IEEE J. Solid State Circuits, 58 (9): 2564-2574 (September 2023)Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization., , , , , , , , , and 31 other author(s). CoRR, (2020)Machine learning for IC design and technology co-optimization in extreme scaling.. VLSI-DAT, page 1. IEEE, (2018)PASAP: power aware structured ASIC placement., and . ISLPED, page 395-400. ACM, (2010)On stress aware active area sizing, gate sizing, and repeater insertion., and . ISPD, page 35-42. ACM, (2009)Editorial: ACM Transactions on Design Automation of Electronics Systems and Beyond., , and . ACM Trans. Design Autom. Electr. Syst., 20 (1): 1:1-1:2 (2014)AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection., , , and . DAC, page 795-800. ACM, (2011)High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths., , , and . DAC, page 161:1-161:6. ACM, (2015)Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis., , , , and . DAC, page 148-153. IEEE, (2007)