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Disambiguation of "Hu, Xiaobo Sharon"

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The application of bit-serial CORDIC computational units to the design of inverse kinematics processors.

, , , and . ICRA, page 1152-1157. IEEE Computer Society, (1988)

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Xiaobo Chen

Xiaobo Zhou

Xiaobo Fan

Xiaobo Yan

Xiaobo Yang

 

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On the use of random walks to estimate correlation in fitness landscapes, and . Computational Statistics & Data Analysis, 28 (2): 131--137 (Aug 7, 1998)System-level reliability modeling for MPSoCs., , , , and . CODES+ISSS, page 297-306. ACM, (2010)Cellular neural networks for image analysis using steep slope devices., , , , , and . ICCAD, page 92-95. IEEE, (2014)Improving tag generation for memory data authentication in embedded processor systems., , , and . ASP-DAC, page 50-55. IEEE, (2016)Approximating the Maximum Sharing Problem., , , , , , , and . WADS, volume 4619 of Lecture Notes in Computer Science, page 52-63. Springer, (2007)Efficient Analog Circuits for Boolean Satisfiability., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (1): 155-167 (2018)Thermal-Aware Task Scheduling for Energy Minimization in Heterogeneous Real-Time MPSoC Systems., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (8): 1269-1282 (2016)Application-level Studies of Cellular Neural Network-based Hardware Accelerators., , , , , and . CoRR, (2019)FeCAM: A Universal Compact Digital and Analog Content Addressable Memory Using Ferroelectric., , , , , , , and . CoRR, (2020)Power and Area Efficient FPGA Building Blocks Based on Ferroelectric FETs., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (5): 1780-1793 (2019)