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Low-Power Architecture for Epileptic Seizure Detection Based on Reduced Complexity DWT.

, , , , and . JETC, 8 (2): 10:1-10:14 (2012)

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A New Double Data Rate(DDR) Dual-Mode Duobinary Transmitter Architecture., , and . VLSI Design, page 12-17. IEEE Computer Society, (2011)Low power and compact mixed-mode signal processing hardware using spin-neurons., , and . ISQED, page 189-195. IEEE, (2013)STT-MRAM for Low Power Access for Read-Intensive Parallel Deep-Learning Architectures., , , and . iNIS, page 61-65. IEEE, (2017)Variation Aware Performance Analysis of TFETs for Low-Voltage Computing., , and . iNIS, page 93-97. IEEE, (2016)Energy efficient hybrid computing systems using spin devices. Purdue University, USA, (2014)Multi-level magnetic RAM using domain wall shift for energy-efficient, high-density caches., , , and . ISLPED, page 64-69. IEEE, (2013)Low Power Implantable Spike Sorting Scheme Based on Neuromorphic Classifier with Supervised Training Engine., , , , and . ISVLSI, page 266-271. IEEE Computer Society, (2017)Hierarchical Temporal Memory Based on Spin-Neurons and Resistive Memory for Energy-Efficient Brain-Inspired Computing., , , and . IEEE Trans. Neural Networks Learn. Syst., 27 (9): 1907-1919 (2016)Spin Neurons: A Possible Path to Energy-Efficient Neuromorphic Computers., , and . CoRR, (2013)Design and Synthesis of Ultra Low Energy Spin-Memristor Threshold Logic., , and . CoRR, (2014)