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Disambiguation of "Kulkarni, Jaydeep P."

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Device/circuit interactions at 22nm technology node.

, , and . DAC, page 97-102. ACM, (2009)

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Jaydeep Belapure

Jagadish Kulkarni

Praveen Kulkarni

Suchita Kulkarni

Aniket Kulkarni

 

Other publications of authors with the same name

A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM., , and . ISLPED, page 171-176. ACM, (2007)A novel slope detection technique for robust STTRAM sensing., , and . ISLPED, page 7-12. IEEE, (2015)Physical Design Strategies for Mitigating Fine-Grained Electromagnetic Side-Channel Attacks., , , , , , , , and . CICC, page 1-2. IEEE, (2021)30.6 Vecim: A 289.13GOPS/W RISC-V Vector Co-Processor with Compute-in-Memory Vector Register File for Efficient High-Performance Computing., , , and . ISSCC, page 492-494. IEEE, (2024)Statistical Analysis of 2T1R Gain-Cell RRAM Bitcell for Area Efficient, High-Performance, and Reliable Multi-level Cell Operation., , and . DRC, page 1-2. IEEE, (2022)Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design., , , and . NANOARCH, page 45-52. IEEE Computer Society, (2011)Neural Network Assisted Compact Model for Accurate Characterization of Cycle-to-cycle Variations in 2-D $h$-BN based RRAM devices., , , , and . DRC, page 103-104. IEEE, (2019)8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation., , , , , , , , , and 2 other author(s). ISSCC, page 1-3. IEEE, (2015)Experimental demonstration of sub-nanosecond switching in 2D hexagonal Boron Nitride resistive memory devices., , , , , , , , and . DRC, page 1-2. IEEE, (2022)Fine-Grained Electromagnetic Side-Channel Analysis Resilient Secure AES Core with Stacked Voltage Domains and Spatio-temporally Randomized Circuit Blocks., , , , , and . ESSCIRC, page 529-532. IEEE, (2022)