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DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool.

K. Chang, J. Ahn, H. Park, K. Choi, and T. Kim. DATE, page 1-6. IEEE, (2023)

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Jinhyung Park

Kwan Park

Shinja Park

June Park

Sungjune Park

Other publications of authors with the same name

Safety Verification of AMS Circuits with Piecewise-Linear System Reachability Analysis.S. Kim, H. Park, and J. Kim. ISOCC, page 203-206. IEEE, (2021)Tightly Linking 3D Via Allocation Towards Routing Optimization for Monolithic 3D ICs.S. Kim, S. Chung, T. Kim, and H. Park. ISLPED, page 26:1-26:6. ACM, (2022)Built-in Self-Test for Inter-Layer Vias in Monolithic 3D ICs.A. Chaudhuri, S. Banerjee, H. Park, B. Ku, K. Chakrabarty, and S. Lim. ETS, page 1-6. IEEE, (2019)Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse.J. Kim, G. Murali, H. Park, E. Qin, H. Kwon, V. Chekuri, N. Rahman, N. Dasari, A. Singh, M. Lee and 6 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 28 (11): 2424-2437 (2020)Advances in Design and Test of Monolithic 3-D ICs.A. Chaudhuri, S. Banerjee, H. Park, J. Kim, G. Murali, E. Lee, D. Kim, S. Lim, S. Mukhopadhyay, and K. Chakrabarty. IEEE Des. Test, 37 (4): 92-100 (2020)Minimum Implant Area-Aware Threshold Voltage Refinement in Pre-Placement.E. Jeong, H. Park, J. Jeong, and T. Kim. MWSCAS, page 232-235. IEEE, (2021)Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse.J. Kim, G. Murali, H. Park, E. Qin, H. Kwon, V. Chekuri, N. Dasari, A. Singh, M. Lee, H. Torun and 5 other author(s). DAC, page 178. ACM, (2019)Synthesizing Asynchronous Circuits toward Practical Use.H. Park, and T. Kim. ISVLSI, page 47-52. IEEE Computer Society, (2016)Comprehensive technique for designing and synthesizing TSV fault-tolerant 3D clock trees.H. Park, and T. Kim. ICCAD, page 691-696. IEEE, (2013)Hybrid asynchronous circuit generation amenable to conventional EDA flow.H. Park, and T. Kim. Integr., (2019)

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Disambiguation of "Park, Heechun"

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DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool.

Please choose a person to relate this publication to

Jinhyung Park

Kwan Park

Shinja Park

June Park

Sungjune Park

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Park, Heechun"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool.

Please choose a person to relate this publication to

Jinhyung Park

Kwan Park

Shinja Park

June Park

Sungjune Park

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool.