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lane serial-link transceiver in 28nm CMOS.

T. Shibasaki, T. Danjo, Y. Ogata, Y. Sakai, H. Miyaoka, F. Terasawa, M. Kudo, H. Kano, A. Matsuda, S. Kawai, T. Arai, H. Higashi, N. Naka, H. Yamaguchi, T. Mori, Y. Koyanagi, and H. Tamura. ISSCC, page 64-65. IEEE, (2016)

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Shigeo Yamaguchi

Fabian Yamaguchi

Ichiro Yamaguchi

Yoko Yamaguchi

Other publications of authors with the same name

Training Deep Neural Networks in 8-bit Fixed Point with Dynamic Shared Exponent Management.H. Yamaguchi, M. Ito, K. Yoda, and A. Ike. DATE, page 1536-1541. IEEE, (2021)F6: Energy-efficient I/O design for next-generation systems.F. O'Mahony, N. Dalt, K. Chang, H. Yamaguchi, C. Kim, and E. Alon. ISSCC, page 520-521. IEEE, (2014)A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution.T. Hashida, Y. Tomita, Y. Ogata, K. Suzuki, S. Suzuki, T. Nakao, Y. Terao, S. Honda, S. Sakabayashi, R. Nishiyama and 6 other author(s). VLSIC, page 1-2. IEEE, (2014)A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS.H. Miyaoka, F. Terasawa, M. Kudo, H. Kano, A. Matsuda, N. Shirai, S. Kawai, T. Shibasaki, T. Danjo, Y. Ogata and 10 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)On-Chip Jitter Measurement Using Jitter Injection in a 28 Gb/s PI-Based CDR.J. Liang, A. Sheikholeslami, H. Tamura, and H. Yamaguchi. IEEE J. Solid State Circuits, 53 (3): 750-761 (2018)A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOS.O. Tyshchenko, A. Sheikholeslami, H. Tamura, Y. Tomita, H. Yamaguchi, M. Kibune, and T. Yamamoto. ISSCC, page 166-167. IEEE, (2010)F3: Emerging technologies for wireline communication.E. Alon, A. Emami, G. den Besten, I. Fujimori, T. Kuroda, M. Nogawa, and H. Yamaguchi. ISSCC, page 504-505. IEEE, (2013)3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS.T. Shibasaki, T. Danjo, Y. Ogata, Y. Sakai, H. Miyaoka, F. Terasawa, M. Kudo, H. Kano, A. Matsuda, S. Kawai and 7 other author(s). ISSCC, page 64-65. IEEE, (2016)10-40 Gb/s I/O design for data communications.K. Chang, T. Carusone, A. Sheikholeslami, B. Payne, M. Moyal, J. Stonick, and H. Yamaguchi. ISSCC, page 502-503. IEEE, (2012)6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOS.W. Rahman, D. Yoo, J. Liang, A. Sheikholeslami, H. Tamura, T. Shibasaki, and H. Yamaguchi. ISSCC, page 120-121. IEEE, (2017)

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Disambiguation of "Yamaguchi, Hisakatsu"

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3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS.

Please choose a person to relate this publication to

Shigeo Yamaguchi

Fabian Yamaguchi

Ichiro Yamaguchi

Ichiro Yamaguchi

Yoko Yamaguchi

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Yamaguchi, Hisakatsu"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS.

Please choose a person to relate this publication to

Shigeo Yamaguchi

Fabian Yamaguchi

Ichiro Yamaguchi

Ichiro Yamaguchi

Yoko Yamaguchi

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS.