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Distributed Fault Simulation with Collaborative Load Balancing for VLSI Circuits.

, , and . Scalable Comput. Pract. Exp., (2011)

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Application Specific True Critical Paths Identification in Sequential Circuits., , , , , and . IOLTS, page 299-304. IEEE, (2019)Parallel Critical Path Tracing Fault Simulation in Sequential Circuits., , , , and . MIXDES, page 305-310. IEEE, (2018)Fault Simulation with Parallel Critical Path Tracing for Combinatorial Circuits Using Structurally Synthesized BDDs., , , and . LATW, page 97-102. IEEE, (2006)On in-system programming of non-volatile memories., , , and . MIXDES, page 408-413. IEEE, (2013)Keynote: Cost-Efficient Reliability for Edge-AI Chips., , , , , , , , , and 3 other author(s). LATS, page 1-2. IEEE, (2024)Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits., , , , and . DSD, page 658-663. IEEE Computer Society, (2010)On coverage of timing related faults at board level., , and . ETS, page 1-2. IEEE, (2016)Asynchronous Fault Detection in IEEE P1687 Instrument Network., , and . NATW, page 73-78. IEEE, (2014)Collaborative Distributed Computing in the Field of Digital Electronics Testing., , and . BASYS, volume 322 of IFIP Advances in Information and Communication Technology, page 145-152. Springer, (2010)Distributed Fault Simulation with Collaborative Load Balancing for VLSI Circuits., , and . Scalable Comput. Pract. Exp., (2011)