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Disambiguation of "Rios, Marco"

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Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing.

, , , , and . DATE, page 1881-1886. IEEE, (2021)

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Luis Silvio Rios Cabrera

Luis Alberto Rios

Juan Ríos Muñoz

Reyes Rios-Cabrera

Róger Humberto Ríos Duarte

 

Other publications of authors with the same name

RRAM-VAC: A Variability-Aware Controller for RRAM-based Memory Architectures., , , and . ASP-DAC, page 181-186. IEEE, (2020)An Associativity-Agnostic in-Cache Computing Architecture Optimized for Multiplication., , , , and . VLSI-SoC, page 34-39. IEEE, (2019)Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing., , , , and . DATE, page 1881-1886. IEEE, (2021)A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication., , , , and . VLSI-SoC, page 1-6. IEEE, (2023)Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems., , , and . ICASSP, page 1549-1552. IEEE, (2020)Write Termination Circuits for RRAM: A Holistic Approach From Technology to Application Considerations., , , , , , , , , and . IEEE Access, (2020)Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference., , , , and . CoRR, (2022)A Flexible In-Memory Computing Architecture for Heterogeneously Quantized CNNs., , , , and . ISVLSI, page 164-169. IEEE, (2021)Functionality Enhanced Memories for Edge-AI Embedded Systems., , , , and . NVMTS, page 1-4. IEEE, (2019)Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge., , , , and . ACM Great Lakes Symposium on VLSI, page 249-254. ACM, (2022)