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A Real-Time Effective Fusion-Based Image Defogging Architecture on FPGA., , , , , , и . ACM Trans. Multim. Comput. Commun. Appl., 17 (3): 93:1-93:21 (2021)Design and Implementation of A High-speed Configurable 2D ML-CFAR Detector., , , , и . ASICON, стр. 1-4. IEEE, (2021)Design and performance evaluation of a 2D-mesh Network on Chip prototype using FPGA., , , , , и . APCCAS, стр. 1264-1267. IEEE, (2008)Scalability Study on Mesh Based Network on Chip., , , , , и . PACIIA (2), стр. 681-685. IEEE Computer Society, (2008)978-0-7695-3490-9.Performance analysis for matrix-multiplication based on an heterogeneous multi-core SoC., , , и . ASICON, стр. 1-4. IEEE, (2015)Design and implementation of homogeneous multi-core system., , , и . ASICON, стр. 788-791. IEEE, (2017)Application-level pipelining on Hierarchical NoC., , , , , , , и . ISCAS, стр. 3873-3876. IEEE, (2010)VLSI Architecture of Video Post-Processing System for MPEG/H.26X., , , , и . NCM, стр. 1520-1525. IEEE Computer Society, (2009)Efficient Softmax Hardware Architecture for Deep Neural Networks., , , , , и . ACM Great Lakes Symposium on VLSI, стр. 75-80. ACM, (2019)A technique of automatic monitor generation based on FSM., , , и . APCCAS, стр. 1775-1778. IEEE, (2008)