Author of the publication

Parallelizing Complex Streaming Applications on Distributed Scratchpad Memory Multicore Architecture.

, , , and . Int. J. Parallel Program., 42 (6): 875-899 (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Hierarchical instruction encoding for VLIW digital signal processors., , , , , , , , and . ISCAS (4), page 3503-3506. IEEE, (2005)Optimized memory access support for data layout conversion on heterogeneous multi-core systems., , , , and . ESTIMedia, page 128-137. IEEE, (2014)Parallelizing Complex Streaming Applications on Distributed Scratchpad Memory Multicore Architecture., , , and . Int. J. Parallel Program., 42 (6): 875-899 (2014)A low-error and Rom-free logarithmic arithmetic unit for embedded 3D graphics applications., , and . VLSI-DAT, page 1-4. IEEE, (2013)A Low-Error, Cost-Efficient Design Procedure for Evaluating Logarithms to Be Used in a Logarithmic Arithmetic Processor., , , , and . IEEE Trans. Computers, 65 (4): 1158-1164 (2016)A unified processor architecture for RISC & VLIW DSP., , , , , , , and . ACM Great Lakes Symposium on VLSI, page 50-55. ACM, (2005)Early Stage Codesign of Multi-PE SIMD Engine: A Case Study on Object Detection., , , and . ICPP Workshops, page 553-560. IEEE Computer Society, (2012)Rapid C to FPGA Prototyping with Multithreaded Emulation Engine., , , and . ISCAS, page 409-412. IEEE, (2007)Parallel object detection on multicore platforms., , and . SiPS, page 075-080. IEEE, (2009)