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Disambiguation of "Mohanty, Basant K."

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Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder.

, , , and . J. Circuits Syst. Comput., 29 (12): 2050186:1-2050186:20 (2020)

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Jitendranath Mohanty

Subhasis Mohanty

Sasank Sekhar Mohanty

Basant Kumar Thakur

Jyoti Ranjan Mohanty

 

Other publications of authors with the same name

Critical-path optimization for efficient hardware realization of lifting and flipping DWTs., , and . ISCAS, page 1186-1189. IEEE, (2015)LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter., , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (5): 1926-1935 (2016)Efficient-Block-Processing Parallel Architecture for Multilevel Lifting 2-D DWT., and . J. Low Power Electron., 9 (1): 37-44 (2013)Concurrent systolic architecture for high-throughput implementation of 3-dimensional discrete wavelet transform., and . ASAP, page 162-166. IEEE Computer Society, (2008)Parallel and Pipeline Architectures for High-Throughput Computation of Multilevel 3-D DWT., and . IEEE Trans. Circuits Syst. Video Techn., 20 (9): 1200-1209 (2010)Memory-access aware work-load distribution for peak-temperature reduction of 3D multi-core embedded systems., , , and . DSP, page 1270-1273. IEEE, (2015)Efficient VLSI architecture for implementation of 1-D discrete wavelet transform based on distributed arithmetic., and . APCCAS, page 1195-1198. IEEE, (2010)Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder., , , and . J. Circuits Syst. Comput., 29 (12): 2050186:1-2050186:20 (2020)Memory-Efficient High-Speed Convolution-Based Generic Structure for Multilevel 2-D DWT., and . IEEE Trans. Circuits Syst. Video Techn., 23 (2): 353-363 (2013)VLSI Architecture for High-Speed / Low-Power Implementation of Multilevel Lifting DWT., and . APCCAS, page 458-461. IEEE, (2006)