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The Influences of Fault Type and Topology on Fault Model Performance and the Implications to Test and Testable Design., and . DAC, page 673-678. IEEE Computer Society Press, (1990)An Efficient Delay Test Generation System for Combinational Logic Circuits., and . DAC, page 522-528. IEEE Computer Society Press, (1990)Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered Binary Decision Diagrams., , , and . DAC, page 417-420. ACM, (1991)Iddq Testing for High Performance CMOS - The Next Ten Years., , , , and . ED&TC, page 578-583. IEEE Computer Society, (1996)Test Generation for Highly Sequential Scan-Testable Circuits Through Logic Transformation., , and . ITC, page 561-565. IEEE Computer Society, (1981)Balanced Excitation and Its Effect on the Fortuitous Detection of Dynamic Defects., , , and . DATE, page 1066-1071. IEEE Computer Society, (2004)Function-Based Dynamic Compaction and its Impact on Test Set Sizes., , and . DFT, page 167-174. IEEE Computer Society, (2003)Using Functional Information and Strategy Switching in Sequential ATPG., and . ICCD, page 254-260. IEEE Computer Society, (1996)On the decline of testing efficiency as fault coverage approaches 100%., , , and . VTS, page 74-83. IEEE Computer Society, (1995)A Deterministic Approach to Adjacency Testing for Delay Faults., and . DAC, page 351-356. ACM Press, (1989)