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Underdesigned and Opportunistic Computing in Presence of Hardware Variability.

, , , , , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (1): 8-23 (2013)

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ASIC Design., and . The VLSI Handbook, CRC Press, (1999)Opportunities and pitfalls in HDL-based system design., , , and . ICCD, page 56-57. IEEE Computer Society, (1996)Ads(3)/CFT(2) to Ads(2)/CFT(1), and . (Jan 28, 2009)Specification and analysis of timing constraints for embedded systems., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (3): 240-256 (1997)Compiler-Directed Cache Line Size Adaptivity., , , , and . Intelligent Memory Systems, volume 2107 of Lecture Notes in Computer Science, page 183-187. Springer, (2000)Timing-driven HW/SW codesign based on task structuring and process timing simulation., , and . CODES, page 203-207. ACM, (1999)BEAR-Data: Analysis and Applications of an Open Multizone Building Dataset., , , , , and . BuildSys@SenSys, page 240-243. ACM, (2023)Marble: collaborative scheduling of batteryless sensors with meta reinforcement learning., , , , and . BuildSys@SenSys, page 140-149. ACM, (2021)Zonal Air Handling in Commercial Buildings., , , , and . BuildSys@SenSys, page 302-303. ACM, (2020)Timing driven co-design of networked embedded systems., , and . ASP-DAC, page 117-122. ACM, (2000)