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Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto's ET-SoC-1 Chip.

D. Ditzel, R. Espasa, N. Aymerich, A. Baum, T. Berg, J. Burr, E. Hao, J. Iyer, M. Izquierdo, S. Jayaratnam, D. Jones, C. Klingner, J. Kim, S. Lee, M. Lupon, G. Magklis, B. Maric, R. Nath, M. Neilly, J. Northcutt, B. Orner, J. Renau, G. Reves, X. Reves, T. Riordan, P. Sanchez, S. Samudrala, G. Sole, R. Tang, T. Thorn, F. Torres, S. Tortella, and D. Yau. HCS, page 1-23. IEEE, (2021)

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Sebastian Roger

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A Performance Study of Out-of-order Vector Architectures and Short Registers.L. Villa, R. Espasa, and M. Valero. International Conference on Supercomputing, page 37-44. ACM, (1998)Larrabee: a many-core x86 architecture for visual computing.L. Seiler, D. Carmean, E. Sprangle, T. Forsyth, M. Abrash, P. Dubey, S. Junkins, A. Lake, J. Sugerman, R. Cavin and 4 other author(s). ACM Trans. Graph., 27 (3): 18 (2008)Exploiting a New Level of DLP in Multimedia Applications.J. Corbal, R. Espasa, and M. Valero. MICRO, page 72-79. ACM/IEEE Computer Society, (1999)Speculative Alias Analysis for Executable Code.M. Fernández, and R. Espasa. IEEE PACT, page 222-231. IEEE Computer Society, (2002)DLP + TLP Processors for the Next Generation of Media Workloads.J. Corbal, R. Espasa, and M. Valero. HPCA, page 219-228. IEEE Computer Society, (2001)Link-Time Path-Sensitive Memory Redundancy Elimination.M. Fernández, and R. Espasa. HPCA, page 300-310. IEEE Computer Society, (2004)Adding a vector unit to a superscalar processor.F. Quintana, J. Corbal, R. Espasa, and M. Valero. International Conference on Supercomputing, page 1-10. ACM, (1999)An ISA Comparison Between Superscalar and Vector Processors.F. Quintana, R. Espasa, and M. Valero. VECPAR, volume 1573 of Lecture Notes in Computer Science, page 548-560. Springer, (1998)A Victim Cache for Vector Registers.R. Espasa, and M. Valero. International Conference on Supercomputing, page 293-300. ACM, (1997)Larrabee: A Many-Core Intel Architecture for Visual Computing.R. Espasa. HiPEAC, volume 5952 of Lecture Notes in Computer Science, page 2. Springer, (2010)

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Disambiguation of "Espasa, Roger"

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Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto's ET-SoC-1 Chip.

Please choose a person to relate this publication to

Sebastian Roger

Susanne Rogers

Gerhard Roger

Christoph Röger

Ralf Röger

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Espasa, Roger"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto's ET-SoC-1 Chip.

Please choose a person to relate this publication to

Sebastian Roger

Susanne Rogers

Gerhard Roger

Christoph Röger

Ralf Röger

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto's ET-SoC-1 Chip.