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Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto's ET-SoC-1 Chip.

D. Ditzel, R. Espasa, N. Aymerich, A. Baum, T. Berg, J. Burr, E. Hao, J. Iyer, M. Izquierdo, S. Jayaratnam, D. Jones, C. Klingner, J. Kim, S. Lee, M. Lupon, G. Magklis, B. Maric, R. Nath, M. Neilly, J. Northcutt, B. Orner, J. Renau, G. Reves, X. Reves, T. Riordan, P. Sanchez, S. Samudrala, G. Sole, R. Tang, T. Thorn, F. Torres, S. Tortella, and D. Yau. HCS, page 1-23. IEEE, (2021)

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Stefanie Marczoch

Langzeitverlauf von 200 Patienten mit kraniofazialen und zervikalen Dystonien bis zu 12 Jahre nach der ersten Botulinumtoxin-BehandlungS. Marczoch. TU München, (2009)

Hans-Peter Marchal

Erna Marcus

Friedrich Marcus

Paul March

Other publications of authors with the same name

Version management alternatives for hardware transactional memory.M. Lupon, G. Magklis, and A. González. MEDEA@PACT, page 69-76. ACM, (2008)A Dynamically Adaptable Hardware Transactional Memory.M. Lupon, G. Magklis, and A. González. MICRO, page 27-38. IEEE Computer Society, (2010)Speculative hardware/software co-designed floating-point multiply-add fusion.M. Lupon, E. Gibert, G. Magklis, S. Samudrala, R. Martínez, K. Stavrou, and D. Ditzel. ASPLOS, page 623-638. ACM, (2014)Architectural support for high-performing hardware transactional memory systems.M. Lupon. Polytechnic University of Catalonia, Spain, (2011)Safe and efficient supervised memory systems.J. Bobba, M. Lupon, M. Hill, and D. Wood. HPCA, page 369-380. IEEE Computer Society, (2011)Ring Oscillator Clocks and Margins.J. Cortadella, M. Lupon, A. Moreno, A. Roca, and S. Sapatnekar. ASYNC, page 19-26. IEEE Computer Society, (2016)Reactive clocks with variability-tracking jitter.J. Cortadella, L. Lavagno, P. Lopez, M. Lupon, A. Moreno, A. Roca, and S. Sapatnekar. ICCD, page 511-518. IEEE Computer Society, (2015)FASTM: A Log-based Hardware Transactional Memory with Fast Abort Recovery.M. Lupon, G. Magklis, and A. González. PACT, page 293-302. IEEE Computer Society, (2009)Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto's ET-SoC-1 Chip.D. Ditzel, R. Espasa, N. Aymerich, A. Baum, T. Berg, J. Burr, E. Hao, J. Iyer, M. Izquierdo, S. Jayaratnam and 23 other author(s). HCS, page 1-23. IEEE, (2021)

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Disambiguation of "Lupon, Marc"

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Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto's ET-SoC-1 Chip.

Please choose a person to relate this publication to

Stefanie Marczoch

Hans-Peter Marchal

Erna Marcus

Friedrich Marcus

Paul March

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Lupon, Marc"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto's ET-SoC-1 Chip.

Please choose a person to relate this publication to

Stefanie Marczoch

Hans-Peter Marchal

Erna Marcus

Friedrich Marcus

Paul March

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto's ET-SoC-1 Chip.