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Disambiguation of "Huang, Ru"

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Quartet: A 22nm 0.09mJ/lnference Digital Compute-in-Memory Versatile AI Accelerator with Heterogeneous Tensor Engines and Off-Chip-Less Dataflow.

, , , , , , , , , and . CICC, page 1-2. IEEE, (2024)

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Ru-Jin Huang

Ru Zhang

Ru Xie

Ru Hao

Tomasz Ru

 

Other publications of authors with the same name

Catching the Missing EM Consequence in Soft Breakdown Reliability in Advanced FinFETs: Impacts of Self-heating, On-State TDDB, and Layout Dependence., , , , , , , , , and 6 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)Sub-20-nm DRAM Technology under Negative Bias Temperature Instability (NBTI): from Characterization to Physical Origin Identification., , , , , , , , , and 5 other author(s). IRPS, page 9. IEEE, (2024)Combinational Access Tunnel FET SRAM for Ultra-Low Power Applications., , , , , , , and . ISCAS, page 1-5. IEEE, (2018)A Spike-Event-Based Neuromorphic Processor with Enhanced On-Chip STDP Learning in 28nm CMOS., , , , , and . ISCAS, page 1-5. IEEE, (2021)Layout-dependent aging mitigation for critical path timing., , , , , , , and . ASP-DAC, page 153-158. IEEE, (2018)Accurate yet Efficient Stochastic Computing Neural Acceleration with High Precision Residual Fusion., , , , , , and . DATE, page 1-6. IEEE, (2023)SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility., , , , , , , , and . DATE, page 1-6. IEEE, (2023)ASTERS: adaptable threshold spike-timing neuromorphic design with twin-column ReRAM synapses., , , , , and . DAC, page 1099-1104. ACM, (2022)AVATAR: an aging- and variation-aware dynamic timing analyzer for application-based DVAFS., , , , and . DAC, page 841-846. ACM, (2022)T-GAN: A deep learning framework for prediction of temporal complex networks with adaptive graph convolution and attention mechanism., , , and . Displays, (2021)